1. Field of the Invention
The present invention relates to a semiconductor and particularly to a semiconductor memory device provided with a buffer writing means for writing data at once into an address area, which includes a plurality of addresses, to be accessed, wherein the buffer writing means conducts a write action of writing simultaneously or continuously data into a group of memory cells determined by the addresses in the address area to be written, a batch verify action of subjecting simultaneously or continuously the memory cells determined by the addresses in the address area to be written to a verify action of examining whether the write action at the memory cells to be written has been completed or not, and repeats the write action and the batch verify action.
2. Description of the Related Art
As its communication has been speeded up and its storage size has been increased, a semiconductor memory device is now demanded for speeding up the writing action. For example, network apparatuses such as mobile telephones require semiconductor memory devices for conducting a write action at higher speeds. Most of the mobile telephones employ flash memories as nonvolatile memory device. Flash memories are commonly of a type of semiconductor memory devices for repeating the verity action and the write action. More specifically, as the write action often fails to be completed after only one time of its execution of writing data into the selected memory cells to be accessed in response to a command of starting the write action received from the outside, its completion can be ensured commonly by attempting a verify action of examining the presence of unwritten memory cells which have failed to be written, a re-write action of writing the data again into the unwritten memory cells, and repeating the verify action and the re-write action a desired number of times. Repeating the verify action and the re-write action is widely employed in not only flash memories or EEPROMs but also any applicable memory cells which are comparatively lower in the speed of the write action or unstable in the write action.
Also, for speeding up the write action, there is proposed a buffer writing means where the write action is conducted at once into a group of memory cells determined by their addresses. The use of such a buffer writing means is advantageous that the switching between the verify action and the re-write action is minimized and neither preparation nor post-action of the write action has to be carried out at each address. In brief, the use of the buffer writing means can comprehensively reduce the duration of time required for the action of writing data as compared with a conventional process of repeating at each address the verify action and the re-write action.
A method of controlling the action of a flash memory (referred to as a conventional device hereinafter) which includes a buffer writing means for repeating the verify action and the re-write action will now be explained referring to FIGS. 12 to 17. FIG. 12 is a block diagram illustrating an arrangement of the conventional device, where a section for conducting the buffer write action only is shown.
The conventional device includes a buffer writing means for writing 16 words of a data (one word consisting of 16 bits, for example) at once into a memory cell array to be targeted. It is also assumed as in a common NOR flash memory that the memory cell at its erased state is at “1” and the memory cell at its written state is at “0”.
An input signal 511 received at an input/output circuit 510 from the outside is transferred to a user interface circuit 520 where it is analyzed. When the input signal 511 is a command for starting the write action, the user interface circuit 520 delivers a command signal 522 to a write buffer circuit 550 for storage of a write data. In response, the write buffer circuit 550 stores the write data prior to the write action.
When the input of the write data has been completed, the user interface circuit 520 delivers another command signal 521 to a write state machine circuit 530 for starting the write action. In response, the write state machine circuit 530 delivers a control signal 532 to a control address circuit 540 for controlling the control address and also other control signals 531 and 533 to an array control circuit 560 and the write buffer circuit 550 respectively for controlling their actions.
Upon receiving the control signal 532, the control address circuit 540 is updated at the control address and delivers a control address signal 541 to both the array control circuit 560 and the write buffer circuit 550. The control address signal 541 is received by the array control circuit 560 for selecting a group of the memory cells to be accessed in memory cell array 570 and by the write buffer circuit 550 for selecting a desired data to be written into the selected memory cells determined by the addresses from the stored data.
The write buffer circuit 550 delivers a data signal 551, which represents the data to be written selected by the control address signal 541, to the array control circuit 560.
In response, the array control signal 560 delivers the control signal 531, the control address signal 541, and the data signal 551 for controlling the action of the memory cell array 570. For example, the write action involves applying write pulses onto the selected memory cells in response to the control signal 561 and the verify action involves commanding an action of reading the selected memory cells and receiving the result of reading from a read data signal 571.
FIG. 13 is a circuitry diagram showing a part of the control address circuit 540. FIG. 14 is a circuitry diagram showing a register cell in the control address circuit 540 shown in FIG. 13. Both a signal DAT [3:0] and a signal WR are contained in the control signal 532. According to the signal DAT [3:0] and the signal WR, the write state machine circuit 530 updates the control address. A signal ADD [3:0] is a portion of the control address signal 541. The register cell shown in FIG. 14 incorporates a simple register circuit. When the signal WR is at “1”, the control address is updated from the signal DAT. The resultant updated control address is released as the signal ADD. When the signal WR returns back to “0”, the updated control address is latched.
FIG. 15 is a circuitry diagram showing an example of the write buffer circuit 550. FIG. 16 is a circuitry diagram showing a register cell REGCELL in the write buffer circuit 550 shown in FIG. 15. The register cell REGCELL incorporates a value sustainable register circuit. For the read action, a node RD is used as pulled up by the data control circuit.
An algorithm for conducting the buffer write action in the conventional device will be explained referring to FIG. 17. It is assumed that the write action fails when it has been executed at a given number of times but not completed.
The action of the algorithm starts with Step S601 for initializing a write counter which counts the number of times of the write action. Step S602 follows for presetting the verify voltage or a voltage to be applied to the word line for the selected memory cells.
At Step S603, the control address is initialized to designate a leading address in the area to be accessed for the buffer write action and clear the write flag. At Step S604, the verify read action is conducted in the selected memory cell determined by the control address.
At Step S605, the result of the verify action is taken. More specifically, the data read out from the selected memory cell is compared with an expected value saved in the write buffer circuit 550 to examine whether the write action has been completed or not and its comparison (the result of the verify action) is used for updating the value saved in the write buffer circuit 550. For example, the value of bit corresponding to the selected memory cell where the write action has been completed is shifted to “1” thus indicating that no more write action is needed at the selected memory cell.
At Step S606, when the value updated at Step S605 and saved in the write buffer circuit 550 indicates that the selected memory cell has to be subjected to the re-write action, the procedure goes to Step S607 for setting up a flag which indicates that the re-write action is needed. When the value updated at Step S605 and saved in the write buffer circuit 550 indicates that no selected memory cell has to be subjected to the re-write action, the flag needs not to be set up.
At Step S608, the control address is incremented. It is then examined at Step S609 whether the verify action has been completed at all the addresses or not. When it is judged that the verify action has not been completed, the procedure returns back to Step S604 for starting the verify action at the succeeding address. Through repeating the steps S604 to S609, the verify action can be conducted at all the addresses.
When the verify action has been completed at all the addresses and it is found at Step S610 that no selected memory cells to be written remain or the write flag is not set up throughout the steps S604 to S609, the buffer write action is ended and its procedure is closed (Step S611). Otherwise, when the memory cell to be written remains or the write flag is set up at any of the addresses throughout the steps S604 to S609, the procedure advances to Step S612 for updating the write counter.
At Step S613, when the count of the write counter reaches the upper limit of the number of repeats of the write action, it is judged that the write action fails and the procedure of the buffer write action is closed (Step S614). When the count of the write counter is lower than the upper limit of the number of repeats of the write action, the procedure goes to Step S615 for setting the write voltage. Since the write voltage to be applied to the selected word line and the selected bit line is different between the verify action and the write action, it has to be switched.
At Step S616, the control address is initialized. At Step S617, the write action at the selected address determined by the control address is then conducted. In case that the write action starts with no selected memory cell to be written allocated to the selected address, it can be canceled any time before the procedure goes to Step S618.
At Step S618, the control address is incremented. It is examined at Step S619 whether the write action at all the addresses has been completed or not. When not, the procedure returns back to Step S617 and the write action is repeated at the succeeding address. The write action at all the addresses can be completed through repeating the steps S617 to S619.
When the write action at all the addresses has been completed, the procedure returns back to Step S602 to start the verify action once again. The batch verify action and the write action can be repeated in this manner.
Another semiconductor memory device equipped with the write buffer circuit for speeding up the write action with the use of a buffer write function is also known where its control algorithm in the circuitry arrangement is simplified in order to further speed up the write action. Such a semiconductor memory device may be controlled, for example, by a masking circuit so that data saved in the write buffer circuit which needs to be not written remain not subjected to the write action over the memory cells (See Japanese Patent Laid-open Publication No. 2004-39112).
However, each of the conventional devices permits the buffer write action to involve the verify action at all the addresses, hence increasing the duration of time required for the batch verify action. FIG. 10 illustrates a table explaining steps of the buffer write action. The “address” column and the “data” column in the table represent addresses for the write action and data to be written at the addresses, respectively. Also, the first to fifth times of the verify action are provided for indicating a combination of (read) data in the memory cell to be read by the batch verify action and (buffer) data in the write buffer circuit 550 rewritten for reflecting the read data.
At the first time of the verify action, all the addresses at 16 words are verified. The buffer data remain unchanged since all the memory cells are at the erase state before the write action. Although the first time of the verify action may be omitted by the action of a means which is added to the conventional device for inhibiting the over-write action, its execution is desirable to detect any accidental over-write action. Similarly at the second time of the verify action, all the addresses at 16 words are verified. Accordingly, the write action is completed over 9 words out of 16 words (as expressed by FFFFh) while the remaining of 7 words (denoted in a parenthesis) is reserved for application of write pulses at the succeeding write action. At the third time of the verify action, all the addresses at 16 words are verified. Then, the write action is completed over 12 words out of 16 words while the remaining of 4 words is reserved for application of write pulses at the succeeding write action. At the fourth time of the verify action, all the addresses at 16 words are verified. Then, the write action is completed over 14 words out of 16 words while the remaining of 2 words is reserved for application of write pulses at the succeeding write action. Finally at the fifth time of the verify action, all the addresses at 16 words are verified. This permits the write action to be completed over all the 16 words. As described, the verify action in the conventional device has to be repeated as many as 80 times, thus increasing the duration of time required for completing the batch verify action.